tools/perf/pmu-events/arch/x86/goldmont/cache.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/x86/goldmont/cache.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/x86/goldmont/cache.json
Extension
.json
Size
70092 bytes
Lines
1119
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
    {
        "BriefDescription": "Requests rejected by the L2Q",
        "Counter": "0,1,2,3",
        "EventCode": "0x31",
        "EventName": "CORE_REJECT_L2Q.ALL",
        "PublicDescription": "Counts the number of demand and L1 prefetcher requests rejected by the L2Q due to a full or nearly full condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to ensure fairness between cores, or to delay a core's dirty eviction when the address conflicts with incoming external snoops.",
        "SampleAfterValue": "200003"
    },
    {
        "BriefDescription": "L1 Cache evictions for dirty data",
        "Counter": "0,1,2,3",
        "EventCode": "0x51",
        "EventName": "DL1.DIRTY_EVICTION",
        "PublicDescription": "Counts when a modified (dirty) cache line is evicted from the data L1 cache and needs to be written back to memory.  No count will occur if the evicted line is clean, and hence does not require a writeback.",
        "SampleAfterValue": "200003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.",
        "Counter": "0,1,2,3",
        "EventCode": "0x86",
        "EventName": "FETCH_STALL.ICACHE_FILL_PENDING_CYCLES",
        "PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ICache miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ICache miss.  Note: this event is not the same as the total number of cycles spent retrieving instruction cache lines from the memory hierarchy.",
        "SampleAfterValue": "200003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Requests rejected by the XQ",
        "Counter": "0,1,2,3",
        "EventCode": "0x30",
        "EventName": "L2_REJECT_XQ.ALL",
        "PublicDescription": "Counts the number of demand and prefetch transactions that the L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the intra-die interconnect (IDI) fabric. The XQ may reject transactions from the L2Q (non-cacheable requests), L2 misses and L2 write-back victims.",
        "SampleAfterValue": "200003"
    },
    {
        "BriefDescription": "L2 cache request misses",
        "Counter": "0,1,2,3",
        "EventCode": "0x2E",
        "EventName": "LONGEST_LAT_CACHE.MISS",
        "PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.",
        "SampleAfterValue": "200003",
        "UMask": "0x41"
    },
    {
        "BriefDescription": "L2 cache requests",
        "Counter": "0,1,2,3",
        "EventCode": "0x2E",
        "EventName": "LONGEST_LAT_CACHE.REFERENCE",
        "PublicDescription": "Counts memory requests originating from the core that reference a cache line in the L2 cache.",
        "SampleAfterValue": "200003",
        "UMask": "0x4f"
    },
    {
        "BriefDescription": "Loads retired that came from DRAM (Precise event capable)",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xD1",
        "EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT",
        "PEBS": "2",
        "PublicDescription": "Counts memory load uops retired where the data is retrieved from DRAM.  Event is counted at retirement, so the speculative loads are ignored.  A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit DRAM, hit in the WCB or receive a HITM response.",
        "SampleAfterValue": "200003",
        "UMask": "0x80"
    },
    {
        "BriefDescription": "Memory uop retired where cross core or cross module HITM occurred (Precise event capable)",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xD1",
        "EventName": "MEM_LOAD_UOPS_RETIRED.HITM",

Annotation

Implementation Notes