tools/perf/pmu-events/arch/x86/goldmont/virtual-memory.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/x86/goldmont/virtual-memory.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/x86/goldmont/virtual-memory.json
Extension
.json
Size
3199 bytes
Lines
72
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
    {
        "BriefDescription": "ITLB misses",
        "Counter": "0,1,2,3",
        "EventCode": "0x81",
        "EventName": "ITLB.MISS",
        "PublicDescription": "Counts the number of times the machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB) for a linear address of an instruction fetch.  It counts when new translation are filled into the ITLB.  The event is speculative in nature, but will not count translations (page walks) that are begun and not finished, or translations that are finished but not filled into the ITLB.",
        "SampleAfterValue": "200003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Memory uops retired that missed the DTLB (Precise event capable)",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xD0",
        "EventName": "MEM_UOPS_RETIRED.DTLB_MISS",
        "PEBS": "2",
        "PublicDescription": "Counts uops retired that had a DTLB miss on load, store or either.  Note that when two distinct memory operations to the same page miss the DTLB, only one of them will be recorded as a DTLB miss.",
        "SampleAfterValue": "200003",
        "UMask": "0x13"
    },
    {
        "BriefDescription": "Load uops retired that missed the DTLB (Precise event capable)",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xD0",
        "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS",
        "PEBS": "2",
        "PublicDescription": "Counts load uops retired that caused a DTLB miss.",
        "SampleAfterValue": "200003",
        "UMask": "0x11"
    },
    {
        "BriefDescription": "Store uops retired that missed the DTLB (Precise event capable)",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xD0",
        "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_STORES",
        "PEBS": "2",
        "PublicDescription": "Counts store uops retired that caused a DTLB miss.",
        "SampleAfterValue": "200003",
        "UMask": "0x12"
    },
    {
        "BriefDescription": "Duration of page-walks in cycles",
        "Counter": "0,1,2,3",
        "EventCode": "0x05",
        "EventName": "PAGE_WALKS.CYCLES",
        "PublicDescription": "Counts every core cycle a page-walk is in progress due to either a data memory operation or an instruction fetch.",
        "SampleAfterValue": "200003",
        "UMask": "0x3"
    },
    {
        "BriefDescription": "Duration of D-side page-walks in cycles",
        "Counter": "0,1,2,3",
        "EventCode": "0x05",
        "EventName": "PAGE_WALKS.D_SIDE_CYCLES",
        "PublicDescription": "Counts every core cycle when a Data-side (walks due to a data operation) page walk is in progress.",
        "SampleAfterValue": "200003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Duration of I-side pagewalks in cycles",
        "Counter": "0,1,2,3",
        "EventCode": "0x05",
        "EventName": "PAGE_WALKS.I_SIDE_CYCLES",
        "PublicDescription": "Counts every core cycle when a Instruction-side (walks due to an instruction fetch) page walk is in progress.",
        "SampleAfterValue": "200003",
        "UMask": "0x2"
    }

Annotation

Implementation Notes