tools/perf/pmu-events/arch/x86/haswellx/cache.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/x86/haswellx/cache.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/x86/haswellx/cache.json
Extension
.json
Size
37086 bytes
Lines
960
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
    {
        "BriefDescription": "L1D data line replacements",
        "Counter": "0,1,2,3",
        "EventCode": "0x51",
        "EventName": "L1D.REPLACEMENT",
        "PublicDescription": "This event counts when new data lines are brought into the L1 Data cache, which cause other lines to be evicted from the cache.",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers unavailability.",
        "Counter": "0,1,2,3",
        "CounterMask": "1",
        "EventCode": "0x48",
        "EventName": "L1D_PEND_MISS.FB_FULL",
        "SampleAfterValue": "2000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "L1D miss outstanding duration in cycles",
        "Counter": "2",
        "EventCode": "0x48",
        "EventName": "L1D_PEND_MISS.PENDING",
        "PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Cycles with L1D load Misses outstanding.",
        "Counter": "2",
        "CounterMask": "1",
        "EventCode": "0x48",
        "EventName": "L1D_PEND_MISS.PENDING_CYCLES",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "AnyThread": "1",
        "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
        "Counter": "2",
        "CounterMask": "1",
        "EventCode": "0x48",
        "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch. HWP are e.",
        "Counter": "0,1,2,3",
        "EventCode": "0x48",
        "EventName": "L1D_PEND_MISS.REQUEST_FB_FULL",
        "SampleAfterValue": "2000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Not rejected writebacks that hit L2 cache",
        "Counter": "0,1,2,3",
        "EventCode": "0x27",
        "EventName": "L2_DEMAND_RQSTS.WB_HIT",
        "PublicDescription": "Not rejected writebacks that hit L2 cache.",
        "SampleAfterValue": "200003",
        "UMask": "0x50"
    },
    {
        "BriefDescription": "L2 cache lines filling L2",
        "Counter": "0,1,2,3",
        "EventCode": "0xF1",
        "EventName": "L2_LINES_IN.ALL",
        "PublicDescription": "This event counts the number of L2 cache lines brought into the L2 cache.  Lines are filled into the L2 cache when there was an L2 miss.",

Annotation

Implementation Notes