tools/perf/pmu-events/arch/x86/haswellx/virtual-memory.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/x86/haswellx/virtual-memory.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/x86/haswellx/virtual-memory.json
Extension
.json
Size
17923 bytes
Lines
436
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
    {
        "BriefDescription": "Load misses in all DTLB levels that cause page walks",
        "Counter": "0,1,2,3",
        "EventCode": "0x08",
        "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
        "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size.",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed",
        "Counter": "0,1,2,3",
        "EventCode": "0x08",
        "EventName": "DTLB_LOAD_MISSES.PDE_CACHE_MISS",
        "PublicDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed.",
        "SampleAfterValue": "100003",
        "UMask": "0x80"
    },
    {
        "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks",
        "Counter": "0,1,2,3",
        "EventCode": "0x08",
        "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
        "PublicDescription": "Number of cache load STLB hits. No page walk.",
        "SampleAfterValue": "2000003",
        "UMask": "0x60"
    },
    {
        "BriefDescription": "Load misses that miss the  DTLB and hit the STLB (2M)",
        "Counter": "0,1,2,3",
        "EventCode": "0x08",
        "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M",
        "PublicDescription": "This event counts load operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.",
        "SampleAfterValue": "2000003",
        "UMask": "0x40"
    },
    {
        "BriefDescription": "Load misses that miss the  DTLB and hit the STLB (4K)",
        "Counter": "0,1,2,3",
        "EventCode": "0x08",
        "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K",
        "PublicDescription": "This event counts load operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.",
        "SampleAfterValue": "2000003",
        "UMask": "0x20"
    },
    {
        "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",
        "Counter": "0,1,2,3",
        "EventCode": "0x08",
        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
        "PublicDescription": "Completed page walks in any TLB of any page size due to demand load misses.",
        "SampleAfterValue": "100003",
        "UMask": "0xe"
    },
    {
        "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
        "Counter": "0,1,2,3",
        "EventCode": "0x08",
        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
        "SampleAfterValue": "2000003",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).",
        "Counter": "0,1,2,3",
        "EventCode": "0x08",
        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
        "PublicDescription": "Completed page walks due to demand load misses that caused 2M/4M page walks in any TLB levels.",
        "SampleAfterValue": "2000003",

Annotation

Implementation Notes