tools/perf/pmu-events/arch/x86/icelake/frontend.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/x86/icelake/frontend.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/x86/icelake/frontend.json
Extension
.json
Size
21736 bytes
Lines
400
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
    {
        "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
        "Counter": "0,1,2,3",
        "EventCode": "0xe6",
        "EventName": "BACLEARS.ANY",
        "PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Stalls caused by changing prefix length of the instruction. [This event is alias to ILD_STALL.LCP]",
        "Counter": "0,1,2,3",
        "EventCode": "0x87",
        "EventName": "DECODE.LCP",
        "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is alias to ILD_STALL.LCP]",
        "SampleAfterValue": "500009",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.",
        "Counter": "0,1,2,3",
        "CounterMask": "1",
        "EdgeDetect": "1",
        "EventCode": "0xab",
        "EventName": "DSB2MITE_SWITCHES.COUNT",
        "PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE speculative transitions.",
        "SampleAfterValue": "100003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
        "Counter": "0,1,2,3",
        "EventCode": "0xab",
        "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
        "PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE.",
        "SampleAfterValue": "100003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Retired Instructions who experienced DSB miss.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc6",
        "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS",
        "MSRIndex": "0x3F7",
        "MSRValue": "0x1",
        "PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc6",
        "EventName": "FRONTEND_RETIRED.DSB_MISS",
        "MSRIndex": "0x3F7",
        "MSRValue": "0x11",
        "PublicDescription": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB miss.",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Retired Instructions who experienced iTLB true miss.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc6",
        "EventName": "FRONTEND_RETIRED.ITLB_MISS",
        "MSRIndex": "0x3F7",
        "MSRValue": "0x14",
        "PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true miss.",
        "SampleAfterValue": "100007",

Annotation

Implementation Notes