tools/perf/pmu-events/arch/x86/icelakex/uncore-interconnect.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/x86/icelakex/uncore-interconnect.json

File Facts

System: Linux kernel
Corpus path: tools/perf/pmu-events/arch/x86/icelakex/uncore-interconnect.json
Extension: .json
Size: 840378 bytes
Lines: 17916
Domain: Support Tooling And Documentation
Bucket: tools
Inferred role: Support Tooling And Documentation: configuration, schema, or hardware description
Status: atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Touches IRQ or DMA behavior; this matters for the representative real-device path.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

[
    {
        "BriefDescription": "Total Write Cache Occupancy : Any Source",
        "Counter": "0,1",
        "EventCode": "0x0F",
        "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "Total Write Cache Occupancy : Any Source : Accumulates the number of reads and writes that are outstanding in the uncore in each cycle.  This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events. : Tracks all requests from any source port.",
        "UMask": "0x1",
        "Unit": "IRP"
    },
    {
        "BriefDescription": "Total Write Cache Occupancy : Snoops",
        "Counter": "0,1",
        "EventCode": "0x0F",
        "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.IV_Q",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "Total Write Cache Occupancy : Snoops : Accumulates the number of reads and writes that are outstanding in the uncore in each cycle.  This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.",
        "UMask": "0x2",
        "Unit": "IRP"
    },
    {
        "BriefDescription": "Total IRP occupancy of inbound read and write requests to coherent memory.",
        "Counter": "0,1",
        "EventCode": "0x0f",
        "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM",
        "PerPkg": "1",
        "PublicDescription": "Total IRP occupancy of inbound read and write requests to coherent memory.  This is effectively the sum of read occupancy and write occupancy.",
        "UMask": "0x4",
        "Unit": "IRP"
    },
    {
        "BriefDescription": "Clockticks of the IO coherency tracker (IRP)",
        "Counter": "0,1",
        "EventCode": "0x01",
        "EventName": "UNC_I_CLOCKTICKS",
        "PerPkg": "1",
        "Unit": "IRP"
    },
    {
        "BriefDescription": "Coherent Ops : CLFlush",
        "Counter": "0,1",
        "EventCode": "0x10",
        "EventName": "UNC_I_COHERENT_OPS.CLFLUSH",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "Coherent Ops : CLFlush : Counts the number of coherency related operations serviced by the IRP",
        "UMask": "0x80",
        "Unit": "IRP"
    },
    {
        "BriefDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline.",
        "Counter": "0,1",
        "EventCode": "0x10",
        "EventName": "UNC_I_COHERENT_OPS.PCITOM",
        "PerPkg": "1",
        "PublicDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline to coherent memory, without a RFO.  PCIITOM is a speculative Invalidate to Modified command that requests ownership of the cacheline and does not move data from the mesh to IRP cache.",
        "UMask": "0x10",
        "Unit": "IRP"
    },
    {
        "BriefDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline.",
        "Counter": "0,1",
        "EventCode": "0x10",
        "EventName": "UNC_I_COHERENT_OPS.RFO",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline to coherent memory.  RFO is a Read For Ownership command that requests ownership of the cacheline and moves data from the mesh to IRP cache.",

Annotation

Atlas domain: Support Tooling And Documentation / tools.
Implementation status: atlas-only.
IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.