tools/perf/pmu-events/arch/x86/ivybridge/frontend.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/x86/ivybridge/frontend.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/x86/ivybridge/frontend.json
Extension
.json
Size
12549 bytes
Lines
286
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
    {
        "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
        "Counter": "0,1,2,3",
        "EventCode": "0xE6",
        "EventName": "BACLEARS.ANY",
        "PublicDescription": "Number of front end re-steers due to BPU misprediction.",
        "SampleAfterValue": "100003",
        "UMask": "0x1f"
    },
    {
        "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
        "Counter": "0,1,2,3",
        "EventCode": "0xAB",
        "EventName": "DSB2MITE_SWITCHES.COUNT",
        "PublicDescription": "Number of DSB to MITE switches.",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles",
        "Counter": "0,1,2,3",
        "EventCode": "0xAB",
        "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
        "PublicDescription": "Cycles DSB to MITE switches caused delay.",
        "SampleAfterValue": "2000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines",
        "Counter": "0,1,2,3",
        "EventCode": "0xAC",
        "EventName": "DSB_FILL.EXCEED_DSB_LINES",
        "PublicDescription": "DSB Fill encountered > 3 DSB lines.",
        "SampleAfterValue": "2000003",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches",
        "Counter": "0,1,2,3",
        "EventCode": "0x80",
        "EventName": "ICACHE.HIT",
        "PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss",
        "Counter": "0,1,2,3",
        "EventCode": "0x80",
        "EventName": "ICACHE.IFETCH_STALL",
        "PublicDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss.",
        "SampleAfterValue": "2000003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Instruction cache, streaming buffer and victim cache misses",
        "Counter": "0,1,2,3",
        "EventCode": "0x80",
        "EventName": "ICACHE.MISSES",
        "PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses.",
        "SampleAfterValue": "200003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
        "Counter": "0,1,2,3",
        "CounterMask": "4",
        "EventCode": "0x79",
        "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",

Annotation

Implementation Notes