tools/perf/pmu-events/arch/x86/jaketown/frontend.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/x86/jaketown/frontend.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/x86/jaketown/frontend.json
Extension
.json
Size
12149 bytes
Lines
291
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
    {
        "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
        "Counter": "0,1,2,3",
        "EventCode": "0xE6",
        "EventName": "BACLEARS.ANY",
        "SampleAfterValue": "100003",
        "UMask": "0x1f"
    },
    {
        "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.",
        "Counter": "0,1,2,3",
        "EventCode": "0xAB",
        "EventName": "DSB2MITE_SWITCHES.COUNT",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
        "Counter": "0,1,2,3",
        "EventCode": "0xAB",
        "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
        "PublicDescription": "This event counts the cycles attributed to a switch from the Decoded Stream Buffer (DSB), which holds decoded instructions, to the legacy decode pipeline.  It excludes cycles when the back-end cannot  accept new micro-ops.  The penalty for these switches is potentially several cycles of instruction starvation, where no micro-ops are delivered to the back-end.",
        "SampleAfterValue": "2000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exceeding way limit.",
        "Counter": "0,1,2,3",
        "EventCode": "0xAC",
        "EventName": "DSB_FILL.ALL_CANCEL",
        "SampleAfterValue": "2000003",
        "UMask": "0xa"
    },
    {
        "BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines.",
        "Counter": "0,1,2,3",
        "EventCode": "0xAC",
        "EventName": "DSB_FILL.EXCEED_DSB_LINES",
        "SampleAfterValue": "2000003",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Cases of cancelling valid DSB fill not because of exceeding way limit.",
        "Counter": "0,1,2,3",
        "EventCode": "0xAC",
        "EventName": "DSB_FILL.OTHER_CANCEL",
        "SampleAfterValue": "2000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.",
        "Counter": "0,1,2,3",
        "EventCode": "0x80",
        "EventName": "ICACHE.HIT",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Instruction cache, streaming buffer and victim cache misses.",
        "Counter": "0,1,2,3",
        "EventCode": "0x80",
        "EventName": "ICACHE.MISSES",
        "PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes unchacheable accesses.",
        "SampleAfterValue": "200003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops.",
        "Counter": "0,1,2,3",

Annotation

Implementation Notes