tools/perf/pmu-events/arch/x86/jaketown/uncore-memory.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/x86/jaketown/uncore-memory.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/x86/jaketown/uncore-memory.json
Extension
.json
Size
31989 bytes
Lines
487
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
    {
        "BriefDescription": "DRAM Activate Count",
        "Counter": "0,1,2,3",
        "EventCode": "0x1",
        "EventName": "UNC_M_ACT_COUNT",
        "PerPkg": "1",
        "PublicDescription": "Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre)",
        "Counter": "0,1,2,3",
        "EventCode": "0x4",
        "EventName": "UNC_M_CAS_COUNT.ALL",
        "PerPkg": "1",
        "UMask": "0xf",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM Reads (RD_CAS + Underfills)",
        "Counter": "0,1,2,3",
        "EventCode": "0x4",
        "EventName": "UNC_M_CAS_COUNT.RD",
        "PerPkg": "1",
        "UMask": "0x3",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre)",
        "Counter": "0,1,2,3",
        "EventCode": "0x4",
        "EventName": "UNC_M_CAS_COUNT.RD_REG",
        "PerPkg": "1",
        "UMask": "0x1",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Underfill Read Issued",
        "Counter": "0,1,2,3",
        "EventCode": "0x4",
        "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
        "PerPkg": "1",
        "UMask": "0x2",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (both Modes)",
        "Counter": "0,1,2,3",
        "EventCode": "0x4",
        "EventName": "UNC_M_CAS_COUNT.WR",
        "PerPkg": "1",
        "UMask": "0xc",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode",
        "Counter": "0,1,2,3",
        "EventCode": "0x4",
        "EventName": "UNC_M_CAS_COUNT.WR_RMM",
        "PerPkg": "1",
        "UMask": "0x8",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode",
        "Counter": "0,1,2,3",
        "EventCode": "0x4",
        "EventName": "UNC_M_CAS_COUNT.WR_WMM",
        "PerPkg": "1",

Annotation

Implementation Notes