tools/perf/pmu-events/arch/x86/knightslanding/cache.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/x86/knightslanding/cache.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/x86/knightslanding/cache.json
Extension
.json
Size
96651 bytes
Lines
2115
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
    {
        "BriefDescription": "Counts the number of MEC requests that were not accepted into the L2Q because of any L2  queue reject condition. There is no concept of at-ret here. It might include requests due to instructions in the speculative path.",
        "Counter": "0,1",
        "EventCode": "0x31",
        "EventName": "CORE_REJECT_L2Q.ALL",
        "SampleAfterValue": "200003"
    },
    {
        "BriefDescription": "This event counts the number of core cycles the fetch stalls because of an icache miss. This is a cumulative count of cycles the NIP stalled for all icache misses.",
        "Counter": "0,1",
        "EventCode": "0x86",
        "EventName": "FETCH_STALL.ICACHE_FILL_PENDING_CYCLES",
        "SampleAfterValue": "200003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Counts the number of L2HWP allocated into XQ GP",
        "Counter": "0,1",
        "EventCode": "0x3E",
        "EventName": "L2_PREFETCHER.ALLOC_XQ",
        "SampleAfterValue": "100007",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Counts the number of L2 cache misses",
        "Counter": "0,1",
        "EventCode": "0x2E",
        "EventName": "L2_REQUESTS.MISS",
        "SampleAfterValue": "200003",
        "UMask": "0x41"
    },
    {
        "BriefDescription": "Counts the total number of L2 cache references.",
        "Counter": "0,1",
        "EventCode": "0x2E",
        "EventName": "L2_REQUESTS.REFERENCE",
        "SampleAfterValue": "200003",
        "UMask": "0x4f"
    },
    {
        "BriefDescription": "Counts the number of MEC requests from the L2Q that reference a cache line (cacheable requests) excluding SW prefetches filling only to L2 cache and L1 evictions (automatically excludes L2HWP, UC, WC) that were rejected - Multiple repeated rejects should be counted multiple times",
        "Counter": "0,1",
        "EventCode": "0x30",
        "EventName": "L2_REQUESTS_REJECT.ALL",
        "SampleAfterValue": "200003"
    },
    {
        "BriefDescription": "Counts all the load micro-ops retired",
        "Counter": "0,1",
        "EventCode": "0x04",
        "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
        "PublicDescription": "This event counts the number of load micro-ops retired.",
        "SampleAfterValue": "200003",
        "UMask": "0x40"
    },
    {
        "BriefDescription": "Counts all the store micro-ops retired",
        "Counter": "0,1",
        "EventCode": "0x04",
        "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
        "PublicDescription": "This event counts the number of store micro-ops retired.",
        "SampleAfterValue": "200003",
        "UMask": "0x80"
    },
    {
        "BriefDescription": "Counts the loads retired that get the data from the other core in the same tile in M state (Precise Event)",
        "Counter": "0,1",
        "Data_LA": "1",
        "EventCode": "0x04",

Annotation

Implementation Notes