tools/perf/pmu-events/arch/x86/meteorlake/memory.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/x86/meteorlake/memory.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/x86/meteorlake/memory.json
Extension
.json
Size
20824 bytes
Lines
436
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
    {
        "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.",
        "Counter": "0,1,2,3",
        "CounterMask": "2",
        "EventCode": "0xa3",
        "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS",
        "SampleAfterValue": "1000003",
        "UMask": "0x2",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",
        "Counter": "0,1,2,3",
        "CounterMask": "6",
        "EventCode": "0xa3",
        "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",
        "SampleAfterValue": "1000003",
        "UMask": "0x6",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to any number of reasons, including an L1 miss, WCB full, pagewalk, store address block or store data block, on a load that retires.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x05",
        "EventName": "LD_HEAD.ANY_AT_RET",
        "SampleAfterValue": "1000003",
        "UMask": "0xff",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a core bound stall including a store address match, a DTLB miss or a page walk that detains the load from retiring.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x05",
        "EventName": "LD_HEAD.L1_BOUND_AT_RET",
        "SampleAfterValue": "1000003",
        "UMask": "0xf4",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DL1 miss.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x05",
        "EventName": "LD_HEAD.L1_MISS_AT_RET",
        "SampleAfterValue": "1000003",
        "UMask": "0x81",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x05",
        "EventName": "LD_HEAD.OTHER_AT_RET",
        "PublicDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases such as pipeline conflicts, fences, etc.",
        "SampleAfterValue": "1000003",
        "UMask": "0xc0",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a pagewalk.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x05",
        "EventName": "LD_HEAD.PGWALK_AT_RET",
        "SampleAfterValue": "1000003",
        "UMask": "0xa0",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a store address match.",
        "Counter": "0,1,2,3,4,5,6,7",

Annotation

Implementation Notes