tools/perf/pmu-events/arch/x86/pantherlake/cache.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/x86/pantherlake/cache.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/x86/pantherlake/cache.json
Extension
.json
Size
76027 bytes
Lines
1565
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
    {
        "BriefDescription": "Counts the number of cache lines replaced in L0 data cache.",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x51",
        "EventName": "L1D.L0_REPLACEMENT",
        "PublicDescription": "Counts L0 data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Cachelines replaced into the L1 d-cache. Successful replacements only (not blocked) and exclude WB-miss case",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x51",
        "EventName": "L1D.L1_REPLACEMENT",
        "PublicDescription": "Counts cachelines replaced into the L1 d-cache.",
        "SampleAfterValue": "1000003",
        "UMask": "0x4",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Cachelines replaced into the L0 and L1 d-cache. Successful replacements only (not blocked) and exclude WB-miss case",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x51",
        "EventName": "L1D.REPLACEMENT",
        "PublicDescription": "Counts cachelines replaced into the L0 and L1 d-cache.",
        "SampleAfterValue": "1000003",
        "UMask": "0x5",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability.",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x49",
        "EventName": "L1D_MISS.FB_FULL",
        "PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
        "SampleAfterValue": "1000003",
        "UMask": "0x2",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x49",
        "EventName": "L1D_MISS.L2_STALLS",
        "PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
        "SampleAfterValue": "1000003",
        "UMask": "0x4",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Number of demand requests that missed L1D cache",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x49",
        "EventName": "L1D_MISS.LOAD",
        "PublicDescription": "Count occurrences (rising-edge) of DCACHE_PENDING sub-event0. Impl. sends per-port binary inc-bit the occupancy increases* (at FB alloc or promotion).",
        "SampleAfterValue": "1000003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Number of L1D misses that are outstanding",
        "Counter": "2",
        "EventCode": "0x48",
        "EventName": "L1D_PENDING.LOAD",
        "PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",
        "SampleAfterValue": "1000003",
        "UMask": "0x1",
        "Unit": "cpu_core"

Annotation

Implementation Notes