tools/perf/pmu-events/arch/x86/pantherlake/memory.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/x86/pantherlake/memory.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/x86/pantherlake/memory.json
Extension
.json
Size
16261 bytes
Lines
330
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
    {
        "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a core bound stall including a store address match, a DTLB miss or a page walk that detains the load from retiring.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x05",
        "EventName": "LD_HEAD.L1_BOUND_AT_RET",
        "SampleAfterValue": "1000003",
        "UMask": "0xf4",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a DL1 miss.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x05",
        "EventName": "LD_HEAD.L1_MISS",
        "SampleAfterValue": "1000003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DL1 miss.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x05",
        "EventName": "LD_HEAD.L1_MISS_AT_RET",
        "SampleAfterValue": "1000003",
        "UMask": "0x81",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to request buffers full or lock in progress.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x05",
        "EventName": "LD_HEAD.WCB_FULL",
        "SampleAfterValue": "1000003",
        "UMask": "0x2",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to request buffers full or lock in progress.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x05",
        "EventName": "LD_HEAD.WCB_FULL_AT_RET",
        "SampleAfterValue": "1000003",
        "UMask": "0x82",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc3",
        "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
        "SampleAfterValue": "1000003",
        "UMask": "0x2",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Number of machine clears due to memory ordering conflicts.",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0xc3",
        "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
        "PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture",
        "SampleAfterValue": "100003",
        "UMask": "0x2",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles.",
        "Counter": "2,3,4,5,6,7,8,9",
        "Data_LA": "1",
        "EventCode": "0xcd",

Annotation

Implementation Notes