tools/perf/pmu-events/arch/x86/pantherlake/virtual-memory.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/x86/pantherlake/virtual-memory.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/x86/pantherlake/virtual-memory.json
Extension
.json
Size
17683 bytes
Lines
341
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
    {
        "BriefDescription": "Counts the number of page walks initiated by a demand load that missed the first and second level TLBs.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x08",
        "EventName": "DTLB_LOAD_MISSES.MISS_CAUSED_WALK",
        "SampleAfterValue": "1000003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Accounts for all page sizes. Will result in a DTLB write from STLB.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x08",
        "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
        "SampleAfterValue": "1000003",
        "UMask": "0x20",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Loads that miss the DTLB and hit the STLB.",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x12",
        "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
        "PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).",
        "SampleAfterValue": "100003",
        "UMask": "0x320",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "CounterMask": "1",
        "EventCode": "0x12",
        "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE",
        "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.",
        "SampleAfterValue": "100003",
        "UMask": "0x10",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to any page size.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x08",
        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
        "PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.",
        "SampleAfterValue": "1000003",
        "UMask": "0xe",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x12",
        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
        "PublicDescription": "Counts completed page walks  (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
        "SampleAfterValue": "100003",
        "UMask": "0xe",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Page walks completed due to a demand data load to a 1G page.",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x12",
        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
        "PublicDescription": "Counts completed page walks  (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
        "SampleAfterValue": "100003",
        "UMask": "0x8",
        "Unit": "cpu_core"
    },

Annotation

Implementation Notes