tools/perf/pmu-events/arch/x86/sapphirerapids/memory.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/x86/sapphirerapids/memory.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/x86/sapphirerapids/memory.json
Extension
.json
Size
33349 bytes
Lines
581
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
    {
        "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",
        "Counter": "0,1,2,3",
        "CounterMask": "6",
        "EventCode": "0xa3",
        "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",
        "SampleAfterValue": "1000003",
        "UMask": "0x6"
    },
    {
        "BriefDescription": "Number of machine clears due to memory ordering conflicts.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc3",
        "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
        "PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture",
        "SampleAfterValue": "100003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
        "Counter": "0,1,2,3",
        "CounterMask": "2",
        "EventCode": "0x47",
        "EventName": "MEMORY_ACTIVITY.CYCLES_L1D_MISS",
        "SampleAfterValue": "1000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
        "Counter": "0,1,2,3",
        "CounterMask": "3",
        "EventCode": "0x47",
        "EventName": "MEMORY_ACTIVITY.STALLS_L1D_MISS",
        "SampleAfterValue": "1000003",
        "UMask": "0x3"
    },
    {
        "BriefDescription": "Execution stalls while L2 cache miss demand cacheable load request is outstanding.",
        "Counter": "0,1,2,3",
        "CounterMask": "5",
        "EventCode": "0x47",
        "EventName": "MEMORY_ACTIVITY.STALLS_L2_MISS",
        "PublicDescription": "Execution stalls while L2 cache miss demand cacheable load request is outstanding (will not count for uncacheable demand requests e.g. bus lock).",
        "SampleAfterValue": "1000003",
        "UMask": "0x5"
    },
    {
        "BriefDescription": "Execution stalls while L3 cache miss demand cacheable load request is outstanding.",
        "Counter": "0,1,2,3",
        "CounterMask": "9",
        "EventCode": "0x47",
        "EventName": "MEMORY_ACTIVITY.STALLS_L3_MISS",
        "PublicDescription": "Execution stalls while L3 cache miss demand cacheable load request is outstanding (will not count for uncacheable demand requests e.g. bus lock).",
        "SampleAfterValue": "1000003",
        "UMask": "0x9"
    },
    {
        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles.",
        "Counter": "1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xcd",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_1024",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x400",
        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles.  Reported latency may be longer than just the memory latency.",
        "SampleAfterValue": "53",
        "UMask": "0x1"
    },
    {

Annotation

Implementation Notes