tools/perf/pmu-events/arch/x86/silvermont/cache.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/x86/silvermont/cache.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/x86/silvermont/cache.json
Extension
.json
Size
31793 bytes
Lines
755
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
    {
        "BriefDescription": "Counts the number of request that were not accepted into the L2Q because the L2Q is FULL.",
        "Counter": "0,1",
        "EventCode": "0x31",
        "EventName": "CORE_REJECT_L2Q.ALL",
        "PublicDescription": "Counts the number of (demand and L1 prefetchers) core requests rejected by the L2Q due to a full or nearly full w condition which likely indicates back pressure from L2Q.  It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link.  The L2Q may also reject transactions  from a core to insure fairness between cores, or to delay a core?s dirty eviction when the address conflicts incoming external snoops.  (Note that L2 prefetcher requests that are dropped are not counted by this event.)",
        "SampleAfterValue": "200003"
    },
    {
        "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.",
        "Counter": "0,1",
        "EventCode": "0x86",
        "EventName": "FETCH_STALL.ICACHE_FILL_PENDING_CYCLES",
        "PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ICache miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ICache miss.  Note: this event is not the same as the total number of cycles spent retrieving instruction cache lines from the memory hierarchy.\r\nCounts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes.  This will include cycles due to an ITLB miss, ICache miss and other events.",
        "SampleAfterValue": "200003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Counts the number of request from the L2 that were not accepted into the XQ",
        "Counter": "0,1",
        "EventCode": "0x30",
        "EventName": "L2_REJECT_XQ.ALL",
        "PublicDescription": "This event counts the number of demand and prefetch transactions that the L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the IDI link. The XQ may reject transactions from the L2Q (non-cacheable requests), BBS (L2 misses) and WOB (L2 write-back victims).",
        "SampleAfterValue": "200003"
    },
    {
        "BriefDescription": "L2 cache request misses",
        "Counter": "0,1",
        "EventCode": "0x2E",
        "EventName": "LONGEST_LAT_CACHE.MISS",
        "PublicDescription": "This event counts the total number of L2 cache references and the number of L2 cache misses respectively.",
        "SampleAfterValue": "200003",
        "UMask": "0x41"
    },
    {
        "BriefDescription": "L2 cache requests from this core",
        "Counter": "0,1",
        "EventCode": "0x2E",
        "EventName": "LONGEST_LAT_CACHE.REFERENCE",
        "PublicDescription": "This event counts requests originating from the core that references a cache line in the L2 cache.",
        "SampleAfterValue": "200003",
        "UMask": "0x4f"
    },
    {
        "BriefDescription": "All Loads",
        "Counter": "0,1",
        "EventCode": "0x04",
        "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
        "PublicDescription": "This event counts the number of load ops retired.",
        "SampleAfterValue": "200003",
        "UMask": "0x40"
    },
    {
        "BriefDescription": "All Stores",
        "Counter": "0,1",
        "EventCode": "0x04",
        "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
        "PublicDescription": "This event counts the number of store ops retired.",
        "SampleAfterValue": "200003",
        "UMask": "0x80"
    },
    {
        "BriefDescription": "Cross core or cross module hitm",
        "Counter": "0,1",
        "EventCode": "0x04",
        "EventName": "MEM_UOPS_RETIRED.HITM",
        "PEBS": "1",
        "PublicDescription": "This event counts the number of load ops retired that got data from the other core or from the other module.",
        "SampleAfterValue": "200003",

Annotation

Implementation Notes