tools/perf/pmu-events/arch/x86/skylake/uncore-interconnect.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/x86/skylake/uncore-interconnect.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/x86/skylake/uncore-interconnect.json
Extension
.json
Size
2797 bytes
Lines
76
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
    {
        "BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
        "Counter": "0,1",
        "EventCode": "0x84",
        "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
        "PerPkg": "1",
        "UMask": "0x1",
        "Unit": "ARB"
    },
    {
        "BriefDescription": "Number of all Core entries outstanding for the memory controller. The outstanding interval starts after LLC miss till return of first data chunk. Accounts for Coherent and non-coherent traffic.",
        "Counter": "0",
        "EventCode": "0x80",
        "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
        "PerPkg": "1",
        "UMask": "0x1",
        "Unit": "ARB"
    },
    {
        "BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
        "Counter": "0",
        "CounterMask": "1",
        "EventCode": "0x80",
        "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST",
        "PerPkg": "1",
        "UMask": "0x1",
        "Unit": "ARB"
    },
    {
        "BriefDescription": "Number of Core Data Read entries outstanding for the memory controller. The outstanding interval starts after LLC miss till return of first data chunk.",
        "Counter": "0",
        "EventCode": "0x80",
        "EventName": "UNC_ARB_TRK_OCCUPANCY.DATA_READ",
        "PerPkg": "1",
        "UMask": "0x2",
        "Unit": "ARB"
    },
    {
        "BriefDescription": "UNC_ARB_TRK_REQUESTS.ALL",
        "Counter": "0,1",
        "EventCode": "0x81",
        "EventName": "UNC_ARB_TRK_REQUESTS.ALL",
        "PerPkg": "1",
        "UMask": "0x1",
        "Unit": "ARB"
    },
    {
        "BriefDescription": "Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent.",
        "Counter": "0,1",
        "EventCode": "0x81",
        "EventName": "UNC_ARB_TRK_REQUESTS.DATA_READ",
        "PerPkg": "1",
        "UMask": "0x2",
        "Unit": "ARB"
    },
    {
        "BriefDescription": "Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent.",
        "Counter": "0,1",
        "EventCode": "0x81",
        "EventName": "UNC_ARB_TRK_REQUESTS.DRD_DIRECT",
        "PerPkg": "1",
        "UMask": "0x2",
        "Unit": "ARB"
    },
    {
        "BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
        "Counter": "0,1",
        "EventCode": "0x81",
        "EventName": "UNC_ARB_TRK_REQUESTS.WRITES",

Annotation

Implementation Notes