tools/perf/pmu-events/arch/x86/tigerlake/uncore-memory.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/x86/tigerlake/uncore-memory.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/x86/tigerlake/uncore-memory.json
Extension
.json
Size
2583 bytes
Lines
57
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
    {
        "BriefDescription": "Counts every read (RdCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.",
        "Counter": "1",
        "EventCode": "0xff",
        "EventName": "UNC_MC0_RDCAS_COUNT_FREERUN",
        "PerPkg": "1",
        "UMask": "0x20",
        "Unit": "imc_free_running_0"
    },
    {
        "BriefDescription": "Counts every 64B read and write request entering the Memory Controller to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.",
        "Counter": "0",
        "EventCode": "0xff",
        "EventName": "UNC_MC0_TOTAL_REQCOUNT_FREERUN",
        "PerPkg": "1",
        "UMask": "0x10",
        "Unit": "imc_free_running_0"
    },
    {
        "BriefDescription": "Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.",
        "Counter": "2",
        "EventCode": "0xff",
        "EventName": "UNC_MC0_WRCAS_COUNT_FREERUN",
        "PerPkg": "1",
        "UMask": "0x30",
        "Unit": "imc_free_running_0"
    },
    {
        "BriefDescription": "Counts every read (RdCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.",
        "Counter": "4",
        "EventCode": "0xff",
        "EventName": "UNC_MC1_RDCAS_COUNT_FREERUN",
        "PerPkg": "1",
        "UMask": "0x20",
        "Unit": "imc_free_running_1"
    },
    {
        "BriefDescription": "Counts every 64B read and write request entering the Memory Controller to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.",
        "Counter": "3",
        "EventCode": "0xff",
        "EventName": "UNC_MC1_TOTAL_REQCOUNT_FREERUN",
        "PerPkg": "1",
        "UMask": "0x10",
        "Unit": "imc_free_running_1"
    },
    {
        "BriefDescription": "Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.",
        "Counter": "5",
        "EventCode": "0xff",
        "EventName": "UNC_MC1_WRCAS_COUNT_FREERUN",
        "PerPkg": "1",
        "UMask": "0x30",
        "Unit": "imc_free_running_1"
    }
]

Annotation

Implementation Notes