tools/perf/tests/shell/lib/perf_metric_validation_rules.json
Source file repositories/reference/linux-study-clean/tools/perf/tests/shell/lib/perf_metric_validation_rules.json
File Facts
- System
- Linux kernel
- Corpus path
tools/perf/tests/shell/lib/perf_metric_validation_rules.json- Extension
.json- Size
- 12578 bytes
- Lines
- 398
- Domain
- Support Tooling And Documentation
- Bucket
- tools
- Inferred role
- Support Tooling And Documentation: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
{
"SkipList": [
"tsx_aborted_cycles",
"tsx_transactional_cycles",
"C2_Pkg_Residency",
"C6_Pkg_Residency",
"C1_Core_Residency",
"C6_Core_Residency",
"tma_false_sharing",
"tma_remote_cache",
"tma_contested_accesses"
],
"RelationshipRules": [
{
"RuleIndex": 1,
"Formula": "a+b",
"TestType": "RelationshipTest",
"RangeLower": "c",
"RangeUpper": "c",
"ErrorThreshold": 5.0,
"Description": "Intel(R) Optane(TM) Persistent Memory(PMEM) bandwidth total includes Intel(R) Optane(TM) Persistent Memory(PMEM) read bandwidth and Intel(R) Optane(TM) Persistent Memory(PMEM) write bandwidth",
"Metrics": [
{
"Name": "pmem_memory_bandwidth_read",
"Alias": "a"
},
{
"Name": "pmem_memory_bandwidth_write",
"Alias": "b"
},
{
"Name": "pmem_memory_bandwidth_total",
"Alias": "c"
}
]
},
{
"RuleIndex": 2,
"Formula": "a+b",
"TestType": "RelationshipTest",
"RangeLower": "c",
"RangeUpper": "c",
"ErrorThreshold": 5.0,
"Description": "DDR memory bandwidth total includes DDR memory read bandwidth and DDR memory write bandwidth",
"Metrics": [
{
"Name": "memory_bandwidth_read",
"Alias": "a"
},
{
"Name": "memory_bandwidth_write",
"Alias": "b"
},
{
"Name": "memory_bandwidth_total",
"Alias": "c"
}
]
},
{
"RuleIndex": 3,
"Formula": "a+b",
"TestType": "RelationshipTest",
"RangeLower": "100",
"RangeUpper": "100",
"ErrorThreshold": 5.0,
"Description": "Total memory read accesses includes memory reads from last level cache (LLC) addressed to local DRAM and memory reads from the last level cache (LLC) addressed to remote DRAM.",
"Metrics": [
{
"Name": "numa_reads_addressed_to_local_dram",
Annotation
- Atlas domain: Support Tooling And Documentation / tools.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.