tools/testing/selftests/arm64/gcs/basic-gcs.c
Source file repositories/reference/linux-study-clean/tools/testing/selftests/arm64/gcs/basic-gcs.c
File Facts
- System
- Linux kernel
- Corpus path
tools/testing/selftests/arm64/gcs/basic-gcs.c- Extension
.c- Size
- 9090 bytes
- Lines
- 413
- Domain
- Support Tooling And Documentation
- Bucket
- tools
- Inferred role
- Support Tooling And Documentation: implementation source
- Status
- source implementation candidate
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
Dependency Surface
limits.hstdbool.hlinux/prctl.hsys/mman.hasm/mman.hasm/hwcap.hlinux/sched.hkselftest.hgcs-util.h
Detected Declarations
function __attribute__function gcs_set_statusfunction read_statusfunction base_enablefunction read_gcspr_el0function enable_writeablefunction enable_push_popfunction enable_allfunction enable_invalidfunction map_guarded_stackfunction test_forkfunction test_vforkfunction main
Annotated Snippet
if (ret == 0) {
if (new_mode != mode) {
ksft_print_msg("Mode set to %lx not %lx\n",
new_mode, mode);
ret = -EINVAL;
}
} else {
ksft_print_msg("Failed to validate mode: %d\n", errno);
}
if (enabling != chkfeat_gcs()) {
ksft_print_msg("%senabled by prctl but %senabled in CHKFEAT\n",
enabling ? "" : "not ",
chkfeat_gcs() ? "" : "not ");
ret = -EINVAL;
}
}
return ret;
}
/* Try to read the status */
static bool read_status(void)
{
unsigned long state;
int ret;
ret = syscall(__NR_prctl, PR_GET_SHADOW_STACK_STATUS, &state, 0, 0, 0);
if (ret != 0) {
ksft_print_msg("Failed to read state: %d\n", errno);
return false;
}
return state & PR_SHADOW_STACK_ENABLE;
}
/* Just a straight enable */
static bool base_enable(void)
{
int ret;
ret = gcs_set_status(PR_SHADOW_STACK_ENABLE);
if (ret) {
ksft_print_msg("PR_SHADOW_STACK_ENABLE failed %d\n", ret);
return false;
}
return true;
}
/* Check we can read GCSPR_EL0 when GCS is enabled */
static bool read_gcspr_el0(void)
{
unsigned long *gcspr_el0;
ksft_print_msg("GET GCSPR\n");
gcspr_el0 = get_gcspr();
ksft_print_msg("GCSPR_EL0 is %p\n", gcspr_el0);
return true;
}
/* Also allow writes to stack */
static bool enable_writeable(void)
{
int ret;
ret = gcs_set_status(PR_SHADOW_STACK_ENABLE | PR_SHADOW_STACK_WRITE);
if (ret) {
ksft_print_msg("PR_SHADOW_STACK_ENABLE writeable failed: %d\n", ret);
return false;
}
ret = gcs_set_status(PR_SHADOW_STACK_ENABLE);
if (ret) {
ksft_print_msg("failed to restore plain enable %d\n", ret);
return false;
}
return true;
}
/* Also allow writes to stack */
static bool enable_push_pop(void)
{
int ret;
ret = gcs_set_status(PR_SHADOW_STACK_ENABLE | PR_SHADOW_STACK_PUSH);
if (ret) {
ksft_print_msg("PR_SHADOW_STACK_ENABLE with push failed: %d\n",
Annotation
- Immediate include surface: `limits.h`, `stdbool.h`, `linux/prctl.h`, `sys/mman.h`, `asm/mman.h`, `asm/hwcap.h`, `linux/sched.h`, `kselftest.h`.
- Detected declarations: `function __attribute__`, `function gcs_set_status`, `function read_status`, `function base_enable`, `function read_gcspr_el0`, `function enable_writeable`, `function enable_push_pop`, `function enable_all`, `function enable_invalid`, `function map_guarded_stack`.
- Atlas domain: Support Tooling And Documentation / tools.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.