tools/testing/selftests/kvm/x86/vmx_pmu_caps_test.c
Source file repositories/reference/linux-study-clean/tools/testing/selftests/kvm/x86/vmx_pmu_caps_test.c
File Facts
- System
- Linux kernel
- Corpus path
tools/testing/selftests/kvm/x86/vmx_pmu_caps_test.c- Extension
.c- Size
- 7206 bytes
- Lines
- 249
- Domain
- Support Tooling And Documentation
- Bucket
- tools
- Inferred role
- Support Tooling And Documentation: implementation source
- Status
- source implementation candidate
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
sys/ioctl.hlinux/bitmap.hkvm_test_harness.hkvm_util.hvmx.h
Detected Declarations
function guest_test_perf_capabilities_gpfunction guest_codefunction for_each_set_bitfunction for_each_set_bitfunction implementationsfunction main
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0
/*
* Test for VMX-pmu perf capability msr
*
* Copyright (C) 2021 Intel Corporation
*
* Test to check the effect of various CPUID settings on
* MSR_IA32_PERF_CAPABILITIES MSR, and check that what
* we write with KVM_SET_MSR is _not_ modified by the guest
* and check it can be retrieved with KVM_GET_MSR, also test
* the invalid LBR formats are rejected.
*/
#include <sys/ioctl.h>
#include <linux/bitmap.h>
#include "kvm_test_harness.h"
#include "kvm_util.h"
#include "vmx.h"
static union perf_capabilities {
struct {
u64 lbr_format:6;
u64 pebs_trap:1;
u64 pebs_arch_reg:1;
u64 pebs_format:4;
u64 smm_freeze:1;
u64 full_width_write:1;
u64 pebs_baseline:1;
u64 perf_metrics:1;
u64 pebs_output_pt_available:1;
u64 pebs_timing_info:1;
};
u64 capabilities;
} host_cap;
/*
* The LBR format and most PEBS features are immutable, all other features are
* fungible (if supported by the host and KVM).
*/
static const union perf_capabilities immutable_caps = {
.lbr_format = -1,
.pebs_trap = 1,
.pebs_arch_reg = 1,
.pebs_format = -1,
.pebs_baseline = 1,
.pebs_timing_info = 1,
};
static const union perf_capabilities format_caps = {
.lbr_format = -1,
.pebs_format = -1,
};
static void guest_test_perf_capabilities_gp(u64 val)
{
u8 vector = wrmsr_safe(MSR_IA32_PERF_CAPABILITIES, val);
__GUEST_ASSERT(vector == GP_VECTOR,
"Expected #GP for value '0x%lx', got %s",
val, ex_str(vector));
}
static void guest_code(u64 current_val)
{
int i;
guest_test_perf_capabilities_gp(current_val);
guest_test_perf_capabilities_gp(0);
for (i = 0; i < 64; i++)
guest_test_perf_capabilities_gp(current_val ^ BIT_ULL(i));
GUEST_DONE();
}
KVM_ONE_VCPU_TEST_SUITE(vmx_pmu_caps);
/*
* Verify that guest WRMSRs to PERF_CAPABILITIES #GP regardless of the value
* written, that the guest always sees the userspace controlled value, and that
* PERF_CAPABILITIES is immutable after KVM_RUN.
*/
KVM_ONE_VCPU_TEST(vmx_pmu_caps, guest_wrmsr_perf_capabilities, guest_code)
{
struct ucall uc;
int r, i;
vcpu_set_msr(vcpu, MSR_IA32_PERF_CAPABILITIES, host_cap.capabilities);
Annotation
- Immediate include surface: `sys/ioctl.h`, `linux/bitmap.h`, `kvm_test_harness.h`, `kvm_util.h`, `vmx.h`.
- Detected declarations: `function guest_test_perf_capabilities_gp`, `function guest_code`, `function for_each_set_bit`, `function for_each_set_bit`, `function implementations`, `function main`.
- Atlas domain: Support Tooling And Documentation / tools.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.